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ASAHI KASEI
[AK4319A]
AK4319A
18Bit SCF DAC
General Description The AK4319A is a high performance 1bit stereo DAC for digital audio systems. A 1bit DAC can achieve monotonicity and low distortion with no adjustment. On chip SCF filter makes the device less affected to the clock jitter and also suppresses the undesirable radio emission noise. The device equips differentially configurated output pins, but either of the pins can be used as single-end. The AK4319A achieves lower Outband noise characteristic and it is suitable for digital broadcasting tuner and other digital audio applications. Features
Sampling Rate Ranging from 8kHz to 54kHz 128 times Oversampling 18bit 8 times Digital Filter 2nd order SCF with High Tolerance to Clock Jitter Differential outputs(Single-end use is available) Digital de-emphasis for 32, 44.1, 48kHz sampling Soft mute I/F format : MSB justified, LSB justified, IIS THD+N: -87dB DR: 92dB Master Clock: 256fs or 384fs Power supply: 4.5 to 5.5V Small Package: 24pin SSOP AK4319 Compatible
M0011-E-01 -1-
1998/6
ASAHI KASEI
[AK4319A]
Ordering Guide AK4319AVM AKD4319A -40+85C Evaluation Board 24pin SSOP(0.65mm pitch)
Pin Layout
Different Points from AK4319 Parameter fs(min) THD+N DR S/N AK4319 10kHz -90dB 96dB 96dB AK4319A 8kHz -87dB 92dB 92dB
M0011-E-01 -2-
1998/6
ASAHI KASEI
[AK4319A]
PIN/FUNCTION
No. 1 2 3 4 5 6 7
Pin Name DIF1 DVDD DVSS LRCK BICK SDATA PD
I/O I I I I I Digital Input Format Pin Digital Power Supply Digital Ground Pin L/R Clock Pin Audio Serial Data Clock Pin
Function (Internal Pull-down pin)
Audio Serial Data Input Pin 2's complement MSB-first data is input on this pin. Power-Down Mode Pin When at "L", the AK4319A is in power-down mode and is held in reset. The AK4319A should always be reset upon power-up. Master Clock Input Pin A crystal can be connected between this pin and XTO, or an external CMOS clock can be input on XTI. Crystal Oscillator Output Pin When an external clock is input, this pin should be left floating. Clock Output Pin The inverted XTI clock is output. Soft Mute Pin (Internal Pull-down pin) When this pin goes "H", soft mute cycle is initiated. When returning "L", the output mute releases. De-emphasis Frequency Select Pin De-emphasis Frequency Select Pin Master Clock Select Pin (Internal Pull-down pin) "L": MCLK=256fs,"H": MCLK=384fs Test Pin (Internal Pull-down pin) Must be left floating or tied to AVSS. Rch Negative analog output pin Rch Positive analog output pin Lch Negative analog output pin Lch Positive analog output pin Voltage Reference Output Pin, 3.0V (typ, respects to AVSS) Normally connected to AVSS with a 0.1uF ceramic capacitor in parallel witha 10uF electrolytic capacitor. Analog Power Supply Pin Analog Ground pin Zero Input Detect Pin Digital Input Format Pin (Internal Pull-down pin)
8
XTI
I
9 10 11
XTO CLKO SMUTE
O O I
12 13 14 15 16 17 18 19 20
DEM0 DEM1 CKS TST AOUTRAOUTR+ AOUTLAOUTL+ VREF
I I I I O O O O O
21 22 23 24
AVDD AVSS DZF DIF0
O I
Note: All input pins except pull-down pins should not be left floating.
M0011-E-01 -3-
1998/6
ASAHI KASEI
[AK4319A]
ABSOLUTE MAXIMUM RATINGS
(AVSS,DVSS=0V; Note 1 ) Parameter Power Supplies: Analog Digital DVDD-AVDD Symbol AVDD DVDD VDA IIN VIND Ta Tstg min -0.3 -0.3 -0.3 -40 -65 max 6.0 6.0 0.3 10 AVDD+0.3 85 150 Units V V V mA V C C
Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature Storage Temperature Note: 1 . All voltages with respect to ground..
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS,DVSS=0V; Note 1 ) Parameter Power Supplies: Analog (Note 2 ) Digital Symbol AVDD DVDD min 4.5 4.5 typ 5.0 5.0 max 5.5 AVDD Units V V
Notes:2 . AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
M0011-E-01 -4-
1998/6
ASAHI KASEI
[AK4319A]
ANALOG CHARACTERISTICS
(Ta=25C; AVDD,DVDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 18bit Input Data; Measurement Bandwidth=10Hz20kHz; RL5k; unless otherwise specified) Parameter Resolution Dynamic Characteristics THD+N Dynamic Range S/N (0dB Output) (-60dB Output, A weight) (A weight) 88 88 90 (Note 3 ) -87 92 92 100 0.15 100 (Note 4 ) 2.60 5 300 2.80 0.3 3.00 -80 dB dB dB dB dB min typ max 18 Units Bits
Interchannel Isolation(1kHz) Interchannel Gain Mismatch DC Accuracy Gain Drift Output Voltage Load Resistance Output Current Power Supplies Power Supply Current Normal Operation (PD="H") AVDD DVDD Power-Down-Mode (PD="L") AVDD+DVDD Power Dissipation (AVDD+DVDD) Normal Operation Power-Down-Mode Power Supply Rejection
ppm/C Vpp k uA
13 4 (Note 5 ) 10 85 50 40
20 7
mA mA uA
135
(Note 5 ) (Note 6 )
mW uW dB
Notes: 3. Measured by AD725C(SHIBASOKU). Averaging mode. Refer to the eva board manual. 4. Full-scale voltage(0dB). When summing the differential outputs by unity gain, AOUT(typ.@0dB)=(AOUT+)-(AOUT-)= 2.80Vpp*VREF/5. 5. In the power-down mode, all digital input pins including clock pins(XTI,,BICK,LRCK) are held DVDD or DVSS. 6. PSR is applied to AVDD,DVDD with 1kHz, 100mVpp.
M0011-E-01 -5-
1998/6
ASAHI KASEI
[AK4319A]
FILTER CHARACTERISTICS
(Ta=25C; AVDD,DVDD=4.5V5.5V; fs=44.1kHz; DEM0="1",DEM1="0") Parameter Digital Filter Passband Stopband Passband Ripple Stopband Attenuation Group Delay Digital Filter + SCF Frequency Response 020.0kHz 0.2 dB (Note 8 ) 0.06dB -6.0dB (Note 7 ) (Note 7 ) PB SB PR SA GD 43 14.7 0 24.1 0.06 22.05 20.0 kHz kHz kHz dB dB 1/fs Symbol min typ max Units
Note: 7. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@0.1dB), SB=0.546*fs. 8. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18bit data of both channels to input register to the output of analog signal.
DIGITAL CHARACTERISTICS
(Ta=25C; AVDD,DVDD=4.55.5V) Parameter High-Level Input Voltage (XTI pin) (All pins except XTI pin) Low-Level Input Voltage (XTI pin) (All pins except XTI pin) AC coupled Input Voltage (XTI pin) High-Level Output Voltage Low-Level Output Voltage Input Leakage Current (Iout=-100uA) (Iout=100uA) (Note 9 ) Symbol VIH1 VIH2 VIL1 VIL2 VAC VOH VOL Iin min 70%DVDD 2.2 1 DVDD-0.5 typ max 30%DVDD 0.8 0.5 10 Units V V V V Vpp V V uA
Notes: 9. TST,SMUTE,DIF0,DIF1,CKS pins have internal pull-down devices, nominally 130k.
M0011-E-01 -6-
1998/6
ASAHI KASEI
[AK4319A]
SWITCHING CHARACTERISTICS
(Ta=25C; AVDD,DVDD=4.55.5V; CL=20pF) Parameter Master Clock Timing Crystal Resonator 256fs: 384fs: External Clock 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High LRCK Frequency Duty Cycle Symbol fCLK fCLK fCLK tCLKL tCLKH fCLK tCLKL tCLKH fs Duty min 7.10 10.70 2.048 28 28 3.072 20 20 8 45 44.1 typ max 13.9 20.7 13.824 Unit MHz MHz MHz MHz ns ns MHz ns ns kHz % ns ns ns ns ns ns ns ns
20.736
54 55
Serial Interface Timing 290 tBCK BICK Period 100 tBCKL BICK Pulse Width Low 100 tBCKH Pulse Width High 40 tBLR BICK rising to LRCK edge (Note 10 ) 40 tLRB LRCK Edge to BICK rising (Note 10 ) 40 tSDH SDATA Hold Time 40 tSDS SDATA Setup Time Reset Timing tPD 100 PD Pulse Width (Note 11 ) Notes: 10. BICK rising edge must not occur at the same time as LRCK edge. 11. The AK4319A can be reset by bringing PD "L" to "H" only upon power up.
M0011-E-01 -7-
1998/6
ASAHI KASEI
[AK4319A]
Timing Diagram
Reset Timing
M0011-E-01 -8-
1998/6
ASAHI KASEI
[AK4319A]
OPERATION OVERVIEW
System Clock
The external clocks which are required to operate the AK4319A are XTI, LRCK, BICK. The master clock(XTI) should be synchronized with LRCK but the phase is not critical. The XTI is used to operate the digital interpolation filter and the delta-sigma modulator. The frequency of XTI is determined by the sampling rate (LRCK) and CKS pin. Table 1 illustrates corresponding clock frequencies. When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Refer to Figure 1 . The master clock can be either a crystal resonator placed across the XTI and XTO pin, or external clock input to the XTI pin with the XTO pin left floating. Not only CMOS clock but sine wave signal with 1Vp-p can be input to the XTI pin by AC coupling. Table 1 illustrates corresponding clock frequencies used in each speed. When using internal oscillation, CLKO can not be used by external circuit at the power-down mode. All external clocks(XTI,BICK,LRCK) should always be present whenever the AK4319A is in normal operation mode(PD="H"). If these clocks are not provided, the AK4319A may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4319A should be reset by PD="L" after these clocks are provided. If the external clocks are not present, the AK4319A should be in the power-down mode(PD="L"). After exiting reset at power-up etc., the AK4319A is in power-down mode until XTI and LRCK are input.
Clock LRCK (fs) BICK MCLK CKS="L" CKS="H"
frequency
8k540kHz
64fs 256fs 384fs
Table 1 . System Clocks
Figure 1 . Internal clock circuit
Figure 2 . X'tal resonator connection
M0011-E-01 -9-
1998/6
ASAHI KASEI
[AK4319A]
Audio Serial Interface Format Data is shifted in via the SDATA pin using BICK and LRCK inputs. Four serial data modes can be selected by the DIF0 and DIF1 pins as shown in Table 2 . In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16 MSB justified formats by zeroing the unused LSBs.
DIF1 DIF0 0 0 1 1 0 1 0 1
Mode 0: 16bit LSB Justified 1: 18bit LSB Justified 2: 18bit MSB Justified 3: I S Compatible
2
BICK 32fs 36fs 36fs
Figure Figure 2 Figure 2 Figure 3
36fs Figure 4 or 32fs
Table 2 . Serial Data Modes
Figure 3 . Mode 0,1 Timing
Figure 4 . Mode 2 Timing
Figure 5 . Mode 3 Timing
M0011-E-01 - 10 -
1998/6
ASAHI KASEI
[AK4319A]
De-emphasis filter The AK4319A includes the digital de-emphasis filter(tc=50/15us) by IIR filter. This filter corresponds to three sampling frequencies(32kHz,44.1kHz,48kHz). De-emphasis is enabled by the following two ways.
DEM1 0 0 1 1
DEM0 0 1 0 1
Mode 44.1kHz OFF 48kHz 32kHz
Table 3 . De-emphasis filter control Zero detection After the input data at both channels are continuously zeros for 8192 LRCK cycles or when the muting period exceeds 8192+1022 LRCK cycles, DZF goes to "H". DZF goes "L" immediately after non zero data is input or soft mute is released. Soft mute operation When SMUTE goes "H", the output signal is attenuated into - during 1022 LRCK cycles. SMUTE is returned to "L", the mute condition is released and the output attenuation gradually changes to 0dB during 1022 LRCK cycles. If the soft mute is released within 1022LRCK cycles, the attenuation is recovered to 0dB with same gradient and cycles. The soft mute function is effective when changing the signal source without stopping the signal transmission.
Notes:
1 { 2 { 3 { 4 {
The output signal is attenuated into - during 1022 LRCK cycles(1022/fs). Analog output corresponding to digital input have the group delay(GD). If the soft mute is released within 1022 LRCK cycles, the attenuation is recovered to 0dB. When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF goes to "H". DZF goes "L" immediately after non-zero data is input. Figure 6 . Soft mute and zero detection
M0011-E-01 - 11 -
1998/6
ASAHI KASEI
[AK4319A]
Power-Down The AK4319A are placed in the power-down mode by bringing PD pin "L" and the analog outputs are floating(Hi-Z). Figure 7 shows an example of the system timing at the power-down and power-up.
1 { 2 { 3 { 4 { 5 {
Analog output has the group delay(GD). When power-down is initiated, analog outputs are set into Hi-Z. Output noise level is about -110dB. Some -50dB of click noise occurs at the transition("") of PD pin. When the master clock is stopped, the AK4319A should have been in the power-down mode. 3 5 If the click noise({ )is a problem, an external mute circuit which generates above timing ({ )is needed. Please refer to Figure 7 . Figure 7 . Power-down/up sequence example
System Reset The AK4319A should be reset once by bringing PD "L" upon power-up. The AK4319A is powered up and the internal timing starts clocking by LRCK "" after exiting reset and power down state by XTI. The AK4319A is in power-down mode until LRCK is input. External mute circuit Some click noise may occur at the transition("") of PD signal. The click noise of PD signal can be avoided by controlling the external mute circuit. The S/N of -110dB could be achieved by muting the analog outputs using DZF signal.
M0011-E-01 - 12 -
1998/6
ASAHI KASEI
[AK4319A]
SYSTEM DESIGN
Figure 8 shows the system connection diagram. An example of external analog filter is shown in Figure 9 . An evaluation board[AKD4319A] is available in order to allow an easy study on the layout of a surrounding circuit.
Figure 8 . Typical Connection Diagram Notes: - Power lines of AVDD and DVDD should be distributed separately from the point with low impedance of regulator etc. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except internal pull-down pins should not be left floating.
1. Grounding and Power Supply Decoupling To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively. AVDD is supplied from analog supply in system and DVDD is supplied from AVDD as shown in Figure 8 . Alternatively if AVDD and DVDD are supplied separately, AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible.
M0011-E-01 - 13 -
1998/6
ASAHI KASEI
[AK4319A]
2. Voltage reference The on-chip voltage reference is output on the VREF pin. An electrolytic capacitor smaller than 10uF in parallel with a 0.1uF ceramic capacitor attached to this pin eliminates the effects of high frequency noise. Especially, the ceramic capacitor should be connected to VREF pin within a few mm as near as possible. No load current may be taken from the VREF output pin. All signals, especially clocks, should be kept away from the VREF pin in order to avoid unwanted coupling into the AK4319A. 3. Analog Outputs The analog signals are output from the differential output pins of each channel, therefore they are summed externally. The analog outputs are the differential voltage,VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-. The bias voltage(Vop/2) for this summing circuit is supplied externally. The output signal range is 1.40V(0.99Vrms, typ) centered at an internal common voltage(AVDD/2). If the summing gain is 1, the output range is 2.80V (1.98Vrms, typ). The input data format is 2's complement. The output voltage(VAOUT) is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal VAOUT is 0V for 0000H(@16bit). DC offsets on analog outputs are eliminated by AC coupling the signals since DAC outputs have a few mV offsets. The noise generated by the delta-sigma modulator beyond the audio passband is sufficiently attenuated by the high speed over-sampling and by the on-chip SCF filter. However, as the outband noise moves into the audible band at low sampling rate, careful attention is required. On Figure 9 , the differential outputs of AK4319A are summed by the 1st-order LPF and the 1.98Vrms output signal range is acquired.
Figure 9 . External LPF example
M0011-E-01 - 14 -
1998/6
ASAHI KASEI 4. Single-end usage
[AK4319A]
The load impedance for the output pin should be higher than 5k. When the AK4319A drives some capacitive load, series resistor(220ohm or more than) should be added the analog output and it should be connected to the analog output pin as near as possible. The output pin which is not used could be left open. When the AK4319A is used as a single-end configuration, the analog characteristics (such as THD+N, DR, S/N) may degrade by 1dB. For single-end operation, in the circuit example of Figure 9 , DC isolation capacitance is added between AOUT- and 10k. Then the 10k resistor which is connected to AOUT+ is removed. In this case, the output level becomes 0.99Vrms. With a single-end configuration, the AK4319A interfaces directly to external circuit such as volume AMP which simplifies the circuit. ,
Figure 10 shows a circuit example for single end operation. The series resistor should be connected to the AOUT pin as near as possible. The operation mode setting in this circuit is as follows. [Operation mode] fs=44.1kHz De-emphasis ON/OFF for fs=44.1kHz Data format: Mode 0, 16bit LSB justified BICK: 64fs MCLK: 256fs [Performancet example] THD+N: -86dB DR,S/N: 91dB
Figure 10 . System Connection External for single end operation
M0011-E-01 - 15 -
1998/6
ASAHI KASEI
[AK4319A]
PACKAGE
z 24pin SSOP (Unit: mm)
NOTE: Dimension "*" does not include mold flash.
Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate
M0011-E-01 - 16 -
1998/6
ASAHI KASEI
[AK4319A]
MARKING
Contents of AAXXXX AA: Lot# XXXX: Date Code
M0011-E-01 - 17 -
1998/6
IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. zAKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. zAny export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. zAKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. zIt is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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